The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a novel design for a stacked silicon nanotube.
Traditional CMOS (Complementary Metal Oxide Semiconductor) fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, research has been devoted to the development of nonplanar transistor architectures. Some non-planar transistor architectures, such as vertical field effect transistors (VFETs) and stacked silicon nanotube field effect transistors (FETs), employ semiconductor channels with various gate-all-around (GAA) technologies to achieve increased device density, greater power efficiency, and some increased performance over lateral devices. In a stacked nanotube FET, the gate stack wraps around the full perimeter of each nanosheet, enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). The wrap-around gate structures and source/drain contacts used in nanotube-based devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.